Advanced non-volatile memory technologies, in particular electrically erasable and programmable non-volatile memories (EEPROMs), may be required to be able to operate with a wide range of supply voltages.
Specifically, EEPROM memories communicating, for example, over a Serial Peripheral Interface bus (SPI) or an Inter-Integrated Circuit (I2C) type series data bus may be required to be compatible with supply voltages varying from 1.6 V to 5.5 V.
The transfer frequency of data over such a bus is related to the value of the supply voltage. Typically, this frequency is 5 MHz for a voltage of 1.6 V and 20 MHz for a voltage of 4.5 V or more.
Yet, data stored in the memory cells of an EEPROM memory are conventionally read by read amplifiers and using methods that are, in particular, influenced by the value of the supply voltage.
A read amplifier converts a measurement of the charge of a memory cell into a digital signal, generally in a voltage-based read mode or in a current-based read mode.
In the voltage-based read mode a constant read current is injected into a bit line, and the resulting voltage on the bit line is compared to a reference voltage.
The read current is well-controlled, because it is injected by the read amplifier.
However, this voltage-based read mode is not recommended when rapid access is required, because of substantial parasitic capacitive coupling between adjacent bit lines.
In the current-based read mode, the bit line is placed at a pre-charge voltage, and the resulting current flowing through the bit line is compared to a reference read current.
This read mode allows a rapid readout, without the drawback of capacitive coupling between bit lines.
However, the current flowing through the bit line is less well-controlled—it may be high if the supply voltage is at a high level and the memory cell highly programmed.
Thus, for a rapid access time at a high supply-voltage level, the reference read current must be sufficiently high.
In general, it is a question of a current that is stable with respect, for example, to the supply voltage and temperature, and originating from a dedicated current source.
At low supply-voltage levels (for example 1.6 V), metal-oxide-semiconductor (MOS) transistors of the read path connecting the memory cell read to the read amplifier are more resistive and pass less current.
These MOS transistors, for example, belong to read-multiplexing and memory-location-decoding devices and generally are used as very resistive, low-control-voltage switches.
Therefore, there is a risk that the current passed by the read path in series with a programmed cell will be lower than the injected read current (in the voltage-based read mode) or than the compared read current (in the current-based read mode).
A programmed cell may thus be read as erased, at low supply-voltage levels.
Conventional solutions consisting in decreasing the read current are limited in terms of access time at high supply-voltage levels. At a low supply-voltage level, indexing the read current lower has the drawback of possibly leading, by way of precaution, to a needlessly low current, resulting in a high access time.